`timescale 1ns/1ps

module  wptr_paf(
                  //output
                  paf,

                 //input
                  wr_clk,
                  wr_rst,
                  wr_clr,
                  wp_bin,
                  rp_s         
                 );
                 
  parameter aw=10;
  parameter n=6;
  parameter max_n=(1<<aw)-n;
  
  
output         paf;                  //high active

input          wr_clk;
input          wr_rst;
input          wr_clr;
input  [aw:0]  wp_bin;
input  [aw:0]  rp_s;


///////////////////////////////////////////////////////////////////////
//local wires
//
reg            paf;

wire	[aw:0]		rp_bin_x;

reg 	[aw:0]		pr_diff;   

    
////////////////////////////////////////////////////////////////////
//
// almost full flag 
//

assign rp_bin_x = rp_s ^ {1'b0, rp_bin_x[aw:1]};	// convert gray to binary


always @(posedge wr_clk or negedge wr_rst)	
if(!wr_rst)	
	pr_diff <= #1 {aw+1{1'b0}};
else if(wr_clr)
	pr_diff <= #1 {aw+1{1'b0}}; 
else
	pr_diff <= #1 wp_bin + ~rp_bin_x +1;
	 
always @(posedge wr_clk or negedge wr_rst)	
if(!wr_rst)	
	paf <= #1 0;
else if(wr_clr)	
	paf <= #1 0; 
else if(pr_diff >= max_n)
	paf <= #1 1;
else
	paf <= #1 0; 	
    
        
endmodule    